Datasheet4U Logo Datasheet4U.com

PE42510A - SPDT High Power UltraCMOS RF Switch

Description

The following specification defines an SPDT (single pole double throw) switch for use in cellular and other wireless applications.

Features

  • HaRP™ technology enhancements to deliver high linearity and exceptional harmonics performance. HaRP™ technology is an innovative feature of the UltraCMOS™ process providing upgraded linearity performance. The PE42510A is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Diagram RFC SPDT High Power UltraC.

📥 Download Datasheet

Datasheet Details

Part number PE42510A
Manufacturer Peregrine Semiconductor
File Size 818.71 KB
Description SPDT High Power UltraCMOS RF Switch
Datasheet download datasheet PE42510A Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
PE42512 RF Switch pSemi
PE42445 High Isolation UltraCMOS SP4T RF Switch pSemi
PE42482 SP8T RF Switch pSemi
PE42726 SPDT RF Switch pSemi
PE4290X (PE-xxxxX) General Purpose Transformers Pulse

Other Datasheets by Peregrine Semiconductor

Part Number Description
PE4251 SPDT RF Switch
PE4250 SPDT RF Switch
PE42520 SPDT RF Switch
PE42521 SPDT RF Switch
PE42522 RF Digital Attenuator

Full PDF Text Transcription

Click to expand full text
Product Specification PE42510A Product Description The following specification defines an SPDT (single pole double throw) switch for use in cellular and other wireless applications. The PE42510A uses Peregrine’s UltraCMOS™ process and it also features HaRP™ technology enhancements to deliver high linearity and exceptional harmonics performance. HaRP™ technology is an innovative feature of the UltraCMOS™ process providing upgraded linearity performance. The PE42510A is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1.
Published: |