PI6C5930 Datasheet Low Skew CMOS PLL Clock Driver

Manufacturer: Pericom Semiconductor (now Diodes Incorporated)

PI6C5930 low skew cmos pll clock driver by Pericom Semiconductor (now Diodes Incorporated) - Datasheet Preview

Datasheet Details

Part number	PI6C5930
Manufacturer	Pericom Semiconductor (now Diodes Incorporated)
File Size	216.77 KB
Description	Low Skew CMOS PLL Clock Driver
Download	PI6C5930 Download (PDF)

General Description

The PI6C5930 clock driver uses a PLL (phase-locked loop) to reduce time skew between a reference clock input (SYNC) and the outputs.

An internal loop filter eliminates the need for external compensation.

This driver generates six clock outputs: Q0 through Q4 running at the same frequency, plus Q/2 which runs at one half the frequency of Q0-Q4.

Overview

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Key Features

Wide frequency range: 100 MHz max.
Five Q and one Q/2 outputs.
Output skew < 250ps (rising edges).
Internal RC loop filter network.
Low noise TTL-compatible outputs.
Balanced drive outputs: +24mA.
Outputs Hi-Z and registers reset when OE = LOW.
PLL bypass for testing and low-frequency.

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