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PI6C5930 - Low Skew CMOS PLL Clock Driver

Product Overview

Pericom Semiconductor

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PI6C5930 Low Skew CMOS PLL Clock Driver by Pericom Semiconductor - Datasheet Preview — Datasheet preview – PI6C5930

Datasheet Details

Part number	PI6C5930
Manufacturer	Pericom Semiconductor
File Size	216.77 KB
Description	Low Skew CMOS PLL Clock Driver
Datasheet	PI6C5930 Datasheet
Additional preview pages of the PI6C5930 datasheet.

Product details

Description

The PI6C5930 clock driver uses a PLL (phase-locked loop) to reduce time skew between a reference clock input (SYNC) and the outputs.

Features

Wide frequency range: 100 MHz max.
Five Q and one Q/2 outputs.
Output skew < 250ps (rising edges).
Internal RC loop filter network.
Low noise TTL-compatible outputs.
Balanced drive outputs: +24mA.
Outputs Hi-Z and registers reset when OE = LOW.
PLL bypass for testing and low-frequency.

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Published: Apr 2, 2010 |