PI90LVT211 Datasheet | Pericom Semiconductor

Features - - - - - - - Meets or Exceeds Requirements of ANSI TIA/EIA-644-1995 Designed for Clocking Rates up to 320MHz Operates from a single 3.3-V Supply Low-Voltage Differential Signaling (LVDS) with Output Voltages of ±350m V into a 100-ohm load Choice between LVDS or TTL clock input Synchronous Enable/Disable Multiplexed clock input - Internal 300 kohm pullup resistor on all control pins - CLK and CLK have 110-ohm termination (PI90LVT211) mon and individual Enable/Disable control 50ps Output-to-Output Skew ±24ps Period Jitter Bus Pins are High Impedance when disabled or with VCC <1.5V TTL Inputs are 5V Tolerant Power Dissipation at 300 MHz P190LV211 is functionally patible with Motorola’s (PECL) MC 10E211/MC100E211 >12k V ESD Protection Packaging (Pb-free & Green available): - 28-pin TSSOP (L) - 28-pin QSOP (Q) Description The PI90LV211 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320 MHz with low skew. The PI90LV211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The device features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock with the high-speed system clock. When LOW the SEL pin will select the differential clock input. Both a mon enable and individual output enables are provided. When asserted the positive output will go LOW on the next negative transition of the CLK (or SCLK) input. The enable function is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. Individual synchronous enable controls and multiplexed clock inputs make this device ideal as the first...