74HC4518 Datasheet | Philips Semiconductors

INTEGRATED CIRCUITS DATA SHEET For a plete data sheet, please also download: - The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications - The IC06 74HC/HCT/HCU/HCMOS Logic Package Information - The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4518 Dual synchronous BCD counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Dual synchronous BCD counter Product specification 74HC/HCT4518 Features - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4518 are high-speed Si-gate CMOS devices and are pin patible with the “4518” of the “4000B” series. They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT4518 are dual 4-bit internally synchronous BCD counters with an active HIGH clock input (n CP0) and an active LOW clock input (n CP1), buffered outputs from all four bit positions (n Q0 to n Q3) and an active HIGH overriding asynchronous master reset input (n MR). The counter advances on either the LOW-to-HIGH transition of n CP0 if n CP1 is HIGH or the HIGH-to-LOW transition of n CP1 if n CP0 is LOW. Either n CP0 or n CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on n MR resets the counter (n Q0 to n Q3 = LOW) independent of n CP0 and n CP1. APPLICATIONS - Multistage synchronous counting - Multistage asynchronous counting - Frequency dividers QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL PARAMETER CONDITIONS TYPICAL HC HCT t PHL/ t PLH t PHL fmax CI CPD propagation delay n CP0, n CP1 to n Qn propagation delay n MR to n Qn maximum clock frequency input capacitance power dissipation capacitance per counter CL = 15 p F; VCC = 5 V notes 1 and 2 20 13 61 3.5...