74HC58
FEATURES
- Output capability: standard
- ICC category: SSI GENERAL DESCRIPTION
The 74HC58 is a high-speed Si-gate CMOS device and is pin patible with low power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate. QUICK REFERENCE DATA GND = 0 V; Tamb = 15 °C; tr = tf = 6 ns SYMBOL t PHL/ t PLH PARAMETER propagation delay 1n to 1Y 2n to 2Y CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in p F VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. input capacitance power dissipation...
