Datasheet4U Logo Datasheet4U.com

LPC2102 - (LPC2101 - LPC2103) Microcontrollers

Download the LPC2102 datasheet PDF. This datasheet also covers the LPC2101 variant, as both devices belong to the same (lpc2101 - lpc2103) microcontrollers family and are provided as variant models within a single manufacturer datasheet.

Description

The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of embedded high-speed flash memory.

Features

  • through output match on all timers, and 32 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 2. Features 2.1 Key features s 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package. s 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation. s ISP/IAP via on-chi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (LPC2101_Philips.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
LPC2101/2102/2103 Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC Rev. 01 — 18 January 2006 Preliminary data sheet 1. General description The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.
Published: |