MJ1410 Description
3 and 4 Data i/p C Data i/p B Data i/p A PositI,. Counter preset ilp bit 2 The counter is preset to the data on these i/ps Counter preset i/p bit 1 on the 3rd positive clock edge following a Counter preset i/p bit 0 negative edge on the 'sync' input. A negative edge on this i/p initiates the counter preset sequence which causes the conversion cycle to start in the register which corresponds to the binary value of...
MJ1410 Key Features
- Single 5V supply
- Three-state outputs
- All inputs TTL patible