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MJ1445 - 2-MBIT PCM SIGNALLING

General Description

This output is set to the level of data bit 1 during time slot 0 of non sync frames.

The data becomes true on the first falling edge of the clock during TS1.

This output is set to the level of data bit 1 during time slot 0 of sync frames.

Key Features

  • 5V ± 5% Supply - 20 mA Typical.
  • Conforms to CCITI Recommendation G732.
  • Synchronising Word Error Monitor.
  • Out of Sync. Alarm.
  • All Inputs and Outputs are TIL Compatible.

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Datasheet Details

Part number MJ1445
Manufacturer Plessey
File Size 112.79 KB
Description 2-MBIT PCM SIGNALLING
Datasheet download datasheet MJ1445 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MJ1445 PCM SYNCHRONISING WORD RECEIVER MJ1445 2 MBIT PCM SIGNALLING CIRCUIT The 2.048 Mbit PCM signalling circuits comprise a group of circuits which will perform the common signalling and error detection functions for a 2.048 MBit 30 channel PCM transmission link operating to the appropriate CCITI recommendations. The circuits are fabricated in N·channel metal gate MOS and operate from a single 5volt supply. Relevant inputs and outputs are TIL compatible. The MJ1445 establishes synchronisation by detecting the synchronising word when it is received at the remote end of the transmission system. The MJ1444 has been designed to generate this synchronisation word at the sending end of the system in accordance with CCITI recommendation G732.