A2S56D30CTP Powerchip Semiconductor Datasheet

A2S56D30CTP Key Features

• Double data rate architecture ; two data transfers per clock cycle
• Bidirectional , data strob (DQS) is transmitted/received with data
• Differential clock input (CLK and /CLK)
• DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
• mands entered on each positive CLK edge
• Data and data mask referenced to both edges of DQS
• 4 bank operation controlled by BA0 , BA1 (Bank Address)
• /CAS latency
• 2.0 / 2.5/ 3 (programmable) ; Burst length
• 2 / 4 / 8 (programmable) Burst type