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ProMOS Technologies

V58C2512SB Datasheet Preview

V58C2512SB Datasheet

High Performance 512M-Bit DDR SDRAM

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V58C2512(804/404/164)SB
HIGH PERFORMANCE 512 Mbit DDR SDRAM
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 8Mbit X 16 (164)
Clock Cycle Time (tCK2.5)
Clock Cycle Time (tCK3)
System Frequency (fCK max)
5
DDR400
6ns
5ns
200 MHz
6
DDR333
6ns
-
166 MHz
75
DDR266
7.5ns
-
133 MHz
Features
High speed data transfer rates with system frequency
up to 200MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2.5, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 60 Ball FBGA AND 66 Pin TSOP II
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V
Power Supply 2.6V ± 0.1V for DDR400
tRAS lockout supported
Concurrent auto precharge option is supported
*Note:
(-5) Supports PC3200 module with 3-3-3 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
(-75) Supports PC2100 module with 2.5-3-3 timing
Description
The V58C2512(804/404/164)SB is a four bank DDR
DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x
32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The
V58C2512(804/404/164)SB achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
60 FBGA
V58C2512(804/404/164)SB Rev.1.4 March 2007
CK Cycle Time (ns)
-5 -6
••
1
-75
Power
Std.
L
Temperature
Mark
Blank




ProMOS Technologies

V58C2512SB Datasheet Preview

V58C2512SB Datasheet

High Performance 512M-Bit DDR SDRAM

No Preview Available !

www.DataSheet4U.com
ProMOS TECHNOLOGIES
V58C2512(804/404/164)SB
Part Number Information
1 23 4 5
6 7 8 9 10
V 58 C 2
51280
ProMOS
ORGANIZATION
& REFRESH
32Mx4, 4K : 12840 8Mx16, 4K : 12816
16Mx8, 4K : 12880
64Mx4, 8K : 25640 16Mx16, 8K : 25616
TYPE
58 : DDR
56 : MOBILE DDR
32Mx8, 8K : 25680
128Mx4, 8K : 51240
64Mx8, 8K : 51280
256Mx4, 8K : G0140
128Mx8, 8K : G0180
8Mx32, 4K : 25632
32Mx16, 8K : 51216
64Mx16, 8K : G0116
11 12 13 14
4 SB
CMOS
VOLTAGE
2 : 2.5 V
1 : 1.8 V
BANKS
2 : 2 BANKS
4 : 4 BANKS
8 : 8 BANKS
I/O
S: SSTL_2
REV LEVEL
A: 1st C: 3rd
B: 2nd D: 4th
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
15 16 17 18
I5
19
TEMPERATURE
BLANK: 0 - 70C
I : -40 - 85C
E : -40 - 125C
SPEED
8 : 125MHz @CL3-3-3
5D : 200MHz @CL2-3-3
75 : 133MHz @CL2.5-3-3 4 : 250MHz @CL4-4-4
7 : 133MHz @CL2-2-2
37 : 266MHz @CL4-4-4
6 : 166MHz @CL2.5-3-3
36 : 275MHz @CL4-4-4
5 : 200MHz @CL3-3-3
33 : 300MHz @CL4-4-4
5B : 200MHz @CL2.5-3-3 3 : 333MHz @CL5-5-5
28 : 350MHz @CL5-5-5
PACKAGE
LEAD
RoHS GREEN PACKAGE
PLATING
DESCRIPTION
T
EI
TSOP
S F J FBGA
B H M BGA
D N Die-stacked TSOP
Z R P Die-stacked FBGA
*RoHS: Restriction of Hazardous Substances
*GREEN: RoHS-compliant and Halogen-Free
V58C2512(804/404/164)SB Rev. 1.4 March 2007
2


Part Number V58C2512SB
Description High Performance 512M-Bit DDR SDRAM
Maker ProMOS Technologies
Total Page 30 Pages
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