HYB18T512400BF Datasheet PDF (512-Mbit Double-Data-Rate-Two SDRAM)

HYB18T512400BF - 512-Mbit Double-Data-Rate-Two SDRAM

This page provides the datasheet information for the HYB18T512400BF, a member of the HYB18T512400B 512-Mbit Double-Data-Rate-Two SDRAM family.

Description

latched at the cross point of differential clocks (CK rising and CK falling).

All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.

Features

The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
Off-Chip-Driver impedance adjustment (OCD) and On.
1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality.
DRAM organizations with 4 and 8 data in/outputs.
Auto-Precharge operation for read and write bursts.
Double-Data-Rate-Two architecture: two data transfers.
Auto-Refresh, Self-Refresh and power saving Powe.

Datasheet Details

Part number	HYB18T512400BF
Manufacturer	Qimonda
File Size	3.73 MB
Description	512-Mbit Double-Data-Rate-Two SDRAM
Datasheet	HYB18T512400BF Datasheet
Additional preview pages of the HYB18T512400BF datasheet.

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Full PDF Text Transcription

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May 2007 HYB18T512400B[C/F] HYB18T512800B[C/F] HYB18T512160B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products www.DataSheet4U.com Internet Data Sheet Rev. 1.1 Internet Data Sheet HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512400B[C/F], HYB18T512160B[C/F], HYB18T512800B[C/F] Revision History: 2007-05, Rev. 1.1 Page All All All Subjects (major changes since last revision) Adapted internet edition Added more product types Qimonda template update Previous Revision: 2007-01, Rev. 1.05 Previous Revision: 2006-02, Rev. 1.04 www.DataSheet4U.com We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.

Published: Dec 17, 2009 |