HYB18T256161BF-28 Datasheet PDF (256-Mbit x16 DDR2 SDRAM) | Download Qimonda AG HYB18T256161BF-28

HYB18T256161BF-28 - 256-Mbit x16 DDR2 SDRAM

This page provides the datasheet information for the HYB18T256161BF-28, a member of the HYB18T256161BF-20 256-Mbit x16 DDR2 SDRAM family.

Description

The 256-Mb DDR2 DRAM is a high-speed Double-Data-Rate-Two CMOS Synchronous DRAM device containing 268,435,456 bits and internally configured as a quad bank DRAM.

The 256-Mb device is organized as 4 Mbit × 16 I/O × 4 banks chip.

Features

The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
Data masks (DM) for write data.
1.8 V ± 0.1V VDD for [.
20/.
25/.
28].
1.8 V ± 0.1V VDDQ for [.
20/.
25/.
28].
Posted CAS by programmable additive latency for better.
DRAM organizations with 16 data in/outputs command and data bus efficiency.
Double Data Rate architecture:.
Off-Chip-Driver impedance adjustment (OCD).

Datasheet Details

Part number	HYB18T256161BF-28
Manufacturer	Qimonda AG
File Size	1.38 MB
Description	256-Mbit x16 DDR2 SDRAM
Datasheet	HYB18T256161BF-28 Datasheet
Additional preview pages of the HYB18T256161BF-28 datasheet.

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Full PDF Text Transcription

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June 2007 www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev. 1.20 Internet Data Sheet www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit Double-Data-Rate-Two SDRAM HYB18T256161BF–20/25/28 Revision History: 2007-06, Rev. 1.20 Page All All 94-101 82-86 All Subjects (major changes since last revision) Typos corrected Final Data Sheet added chapter 7 explaining AC timing measurement condition (reference load ; slew rate ; set up & hold timing references ; derating values for input /command ,data ) setup & hold timings are changed with reference to Industrial standard definition removed all the occurances of RDQS as it in not used in graphics (x16) Previous Revision: Rev. 1.0, 2006-09 Previous Revision: Rev. 0.

Published: Apr 24, 2010 |