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70V05L - DUAL-PORT STATIC RAM

Download the 70V05L datasheet PDF. This datasheet also covers the 70V05S variant, as both devices belong to the same dual-port static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM.

The IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bitor-morewordsystems.

Key Features

  • True Dual-Ported memory cells which allow simultaneous reads of the same memory location.
  • High-speed access.
  • Commercial: 15ns (max. ).
  • Industrial: 20ns (max. ).
  • Low-power operation.
  • IDT70V05L Active: 380mW (typ. ) Standby: 660μW (typ. ).
  • IDT70V05 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device.
  • M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave.
  • Interr.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (70V05S-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 70V05L
Manufacturer Renesas
File Size 478.96 KB
Description DUAL-PORT STATIC RAM
Datasheet download datasheet 70V05L Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM 70V05S/L Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Commercial: 15ns (max.) – Industrial: 20ns (max.) ◆ Low-power operation – IDT70V05L Active: 380mW (typ.) Standby: 660μW (typ.) ◆ IDT70V05 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave ◆ Interrupt Flag ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ TTL-compatible, single 3.3V (±0.