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71124 Datasheet

CMOS Static RAM

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CMOS Static RAM
1 Meg (128K x 8-Bit)
Revolutionary Pinout
71124
Features
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise.
Equal access and cycle times
– Commercial: 12/15/20ns
– Industrial: 15/20ns
One Chip Select plus one Output Enable pin
Bidirectional inputs and outputs directly TTL-compatible
Low power consumption via chip deselect
Available in a 32-pin 400 mil Plastic SOJ.
Description
The IDT71124 is a 1,048,576-bit high-speed static RAM organized as
128K x 8. It is fabricated using high-performance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuitdesigntechniques,providesa cost-effectivesolutionforhigh-speed
memory needs. The JEDEC centerpower/GND pinout reduces noise
generation and improves system performance.
The IDT71124 has an output enable pin which operates as fast as 6ns,
with address access times as fast as 12ns available. All bidirectional inputs
and outputs of the IDT71124 are TTL-compatible and operation is from
a single 5V supply. Fully static asynchronous circuitry is used; no clocks
or refreshes are required for operation.
The IDT71124 is packaged in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
A0
A16
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O0 - I/O7
8
8
WE
OE CONTROL
CS LOGIC
I/O CONTROL
8
,
3514 drw 01
Feb.27.20
1


Renesas Electronics Components Datasheet

71124 Datasheet

CMOS Static RAM

No Preview Available !

71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout
Pin Configuration
A0
A1
A2
A3
CS
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5 71124
6 PBG32
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
,
3514 drw 02
SOJ
Top View
Truth Table(1,2)
CS OE WE
I/O
Function
L L H DATAOUT Read Data
L X L DATAIN Write Data
L H H High-Z Output Disabled
H X X High-Z Deselected - Standby (ISB)
VHC(3 )
X
X High-Z Deselected - Standby (ISB1)
NOTES:
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VCC -0.2V.
3. Other inputs VHC or VLC.
3514 tbl 01
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
Rating
Value
Unit
VTERM(2)
Terminal Voltage with
Respect to GND
-0.5 to +7.0(2)
V
TA
Operating Temperature
0 to +70
oC
TBIAS
Temperature
Under Bias
-55 to +125
oC
TSTG Storage
Temperature
-55 to +125
oC
PT Power Dissipation
1.25 W
IOUT DC Output Current
50 mA
NOTES:
3514 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VTERMmust not exceed Vcc + 0.5V.
Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max. Unit
CIN Input Capacitance
VIN = 3dV
8 pF
CI/O I/O Capacitance
VOUT = 3dV
8 pF
NOTE:
3514 tbl 03
1. This parameter is guaranteed by device characterization, but is not production tested.
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature
GND
VCC
Commercial
0°C to +70°C
0V 5.0V ± 10%
Industrial
–40°C to +85°C
0V 5.0V ± 10%
3514 tbl 04
Recommended DC Operating
Conditions
Symbol
Parameter
Min. Typ. Max.
Unit
VCC Supply Voltage
4.5 5.0 5.5 V
GND Ground
0 0 0V
VIH Input High Voltage
2.2 ____ VCC +0.5 V
VIL Input Low Voltage
-0.5(1)
____
0.8
V
NOTE:
3514 tbl 05
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
Feb.27.20
6.422


Part Number 71124
Description CMOS Static RAM
Maker Renesas
Total Page 9 Pages
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