71V2556SA, 71V2556S Datasheet - Renesas

71V2556SA 3.3V Synchronous SRAMs

The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are .

71V2556SA Features

* 128K x 36 memory configurations

* Supports high performance system speed - 166 MHz (3.5 ns Clock-to-Data Access)

* ZBTTM Feature - No dead cycles between write and read cycles

* Internally synchronized output buffer enable eliminates the need to control OE

* Single R/W (READ/WR

71V2556S-Renesas.pdf