71V2556S - 3.3V Synchronous SRAMs

Product Overview

Renesas

Part number	71V2556S
Manufacturer	Renesas
File Size	300.74 KB
Description	3.3V Synchronous SRAMs
Datasheet	71V2556S Datasheet
Additional preview pages of the 71V2556S datasheet.

The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM.

It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.

128K x 36 memory configurations.
Supports high performance system speed - 166 MHz (3.5 ns Clock-to-Data Access).
ZBTTM Feature - No dead cycles between write and read cycles.
Internally synchronized output buffer enable eliminates the need to control OE.
Single R/W (READ/WRITE) control pin.
Positive clock-edge triggered address, data, and control signal registers for fully pipelined.

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Published: Jul 22, 2023 |