71V2556SA Overview
The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.
71V2556SA Key Features
- 128K x 36 memory configurations
- Supports high performance system speed
- 166 MHz
- ZBTTM Feature
- No dead cycles between write and read
- Internally synchronized output buffer enable eliminates the
- Single R/W (READ/WRITE) control pin
- Positive clock-edge triggered address, data, and control