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72V225 Datasheet

3.3 VOLT CMOS SyncFIFO

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3.3 VOLT CMOS SyncFIFOTM
IDT72V205, IDT72V215,
256 x 18, 512 x 18, 1,024 x 18,
IDT72V225, IDT72V235,
2,048 x 18, and 4,096 x 18
IDT72V245
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
256 x 18-bit organization array (IDT72V205)
512 x 18-bit organization array (IDT72V215)
1,024 x 18-bit organization array (IDT72V225)
2,048 x 18-bit organization array (IDT72V235)
4,096 x 18-bit organization array (IDT72V245)
10 ns read/write cycle time
5V input tolerant
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full flags
Easily expandable in depth and width
Asynchronous or coincident Read and Write Clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output enable puts output data bus in high-impedance state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72V205/72V215/72V225/72V235/72V245 are functionally com-
patible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB,
designed to run off a 3.3V supply for exceptionally low power consumption.
These devices are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs are applicable
for a wide variety of data buffering needs, such as optical disk controllers, Local
Area Networks (LANs), and interprocessor communication.
These FIFOs have 18-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is read
into the synchronous FIFO on every clock when WEN is asserted. The output
port is controlled by another clock pin (RCLK) and another enable pin (REN).
The Read Clock(RCLK) can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (OE) is provided on the read port for three-state control
of the output.
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK
FL
WXI
(HF)/WXO
RXI
RXO
RS
WRITE CONTROL
LOGIC
WRITE POINTER
EXPANSION LOGIC
RESET LOGIC
D0-D17
INPUT REGISTER
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
OUTPUT REGISTER
OE
Q0-Q17
LD
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
FF/IR
PAF
EF/OR
PAE
HF/(WXO)
RCLK REN
4294 drw 01
IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2018
DSC-4294/8


Renesas Electronics Components Datasheet

72V225 Datasheet

3.3 VOLT CMOS SyncFIFO

No Preview Available !

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
programmable flags is controlled by a simple state machine, and is initiated by
asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO
is used in a single device configuration.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall-Through (FWFT) mode.
In IDT Standard Mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or
First Word Fall Through mode (FWFT). The XI and XO pins are used to expand
the FIFOs. In depth expansion configuration, First Load (FL) is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using
high-speed submicron CMOS technology.
PIN CONFIGURATIONS
PIN 1
D15
1
D14
2
D13
3
D12
4
D11
5
D10
6
D9
7
D8
8
D7
9
D6
10
D5
11
D4
12
D3
13
D2
14
D1
15
D0
16
48
Q14
47
Q13
46
GND
45
Q12
44
Q11
43
VCC
42
Q10
41
Q9
40
GND
39
Q8
38
Q7
37
Q6
36
Q5
35
GND
34
Q4
33
VCC
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
4294 drw 02
2


Part Number 72V225
Description 3.3 VOLT CMOS SyncFIFO
Maker Renesas
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72V225 Datasheet PDF






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