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8432I-51 Datasheet

Crystal-to-3.3V Differential LVPECL Frequency Synthesizer

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700MHz, Crystal-to-3.3V Differential
LVPECL Frequency Synthesizer
8432I-51
DATA SHEET
GENERAL DESCRIPTION
The 8432I-51 is a general purpose, dual output Crystal-to-3.3V
Differential LVPECL High Frequency Synthesizer. The 8432I-51
has a selectable REF_CLK or crystal input. The VCO operates
at a frequency range of 250MHz to 700MHz. The VCO frequency
is programmed in steps equal to the value of the input reference
or crystal frequency. The VCO and output frequency can be pro-
grammed using the serial or parallel interface to the configuration
logic. The low phase noise characteristics of the 8432I-51 make it
an ideal clock source for Gigabit Ethernet, Fibre Channel 1 and 2,
and Infiniband applications.
FEATURES
Dual differential 3.3V LVPECL outputs
Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_CLK
Output frequency range: 31.25MHz to 700MHz
Crystal input frequency range: 12MHz to 25MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming counter and
output dividers
RMS period jitter: 3.5ps (maximum)
Cycle-to-cycle jitter: 40ps (maximum)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
8432I-51 REVISION A 11/18/15
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
M5 1
24 XTAL_OUT
M6 2
23 REF_CLK
M7 3
22 XTAL_SEL
M8 4
N0 5
8432I-51
21 VCCA
20 S_LOAD
N1 6
19 S_DATA
nc 7
18 S_CLOCK
VEE 8
17 MR
9 10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
1
©2015 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

8432I-51 Datasheet

Crystal-to-3.3V Differential LVPECL Frequency Synthesizer

No Preview Available !

8432I-51 DATA SHEET
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes oper-
ation using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The 8432I-51 features a fully integrated PLL and therefore, re-
quires no external components for setting the loop bandwidth.
A fundamental crystal is used as the input to the on-chip oscil-
lator. The output of the oscillator is fed into the phase detector.
A 25MHz crystal provides a 25MHz phase detector reference fre-
quency. The VCO of the PLL operates over a range of 250MHz to
700MHz. The output of the M divider is also applied to the phase
detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the 8432I-51 support two input
modes to program the M divider and N output divider. The two
input operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode, the nP_LOAD
input is initially LOW. The data on inputs M0 through M8 and N0
and N1 is passed directly to the M divider and N output divider.
On the LOW-to-HIGH transition of the nP_LOAD input, the data
is latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. As a re-
sult, the M and N bits can be hardwired to set the M divider and
N output divider to a specific default state that will automatically
occur during power-up. The TEST output is LOW when operating in
the parallel input mode. The relationship between the VCO frequen-
cy, the crystal frequency and the M divider is defined as follows:
fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz
reference are defined as 10 M 28. The frequency out is defined
as follows: FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift reg-ister
are loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each ris-ing edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1 T0
00
01
10
11
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
2
LVPECL FREQUENCY SYNTHESIZER
REVISION B 11/18/15


Part Number 8432I-51
Description Crystal-to-3.3V Differential LVPECL Frequency Synthesizer
Maker Renesas
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