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854S006 Datasheet

Differential-to-LVDS Fanout Buffer

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Low Skew, 1-to-6,
Differential-to-LVDS Fanout Buffer
854S006
Datasheet
Description
The 854S006 is a low skew, high performance 1-to-6,
Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept
most standard differential input levels. The 854S006 is
characterized to operate from either a 2.5V or a 3.3V power
supply. Guaranteed output and part-to-part skew characteristics
make the 854S006 ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
Six differential LVDS outputs
One differential clock input pair
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
Output Skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Q0
nQ0
CLK
nCLK
Pull-up
Pull-down
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Pin Assignment
nCLK 1
CLK 2
VDD
3
VDDO
4
Q0 5
nQ0 6
GND 7
Q1 8
nQ1 9
VDDO
10
Q2 11
nQ2 12
24 GND
23 GND
22
VDD
21
VDDO
20 nQ5
19 Q5
18 GND
17 nQ4
16 Q4
15
VDDO
14 nQ3
13 Q3
©2017 Integrated Device Technology, Inc.
1
April 11, 2017


Renesas Electronics Components Datasheet

854S006 Datasheet

Differential-to-LVDS Fanout Buffer

No Preview Available !

Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Type[a]
Description
1
nCLK
Input (PD) Inverting differential clock input.
2
CLK
Input (PU) Non-inverting differential clock input.
3, 22
4, 10, 15, 21
5, 6
VDD
VDDO
Q0, nQ0
Power
Power
Output
Positive supply pins.
Output supply pins.
Differential output pair. LVDS interface levels.
7, 18, 23, 24
GND
Power
Power supply ground.
8, 9
Q1, nQ1
Output
Differential output pair. LVDS interface levels.
11, 12
Q2, nQ2
Output
Differential output pair. LVDS interface levels.
13, 14
Q3, nQ3
Output
Differential output pair. LVDS interface levels.
16, 17
Q4, nQ4
Output
Differential output pair. LVDS interface levels.
19, 20
Q5, nQ5
Output
Differential output pair. LVDS interface levels.
[a] Pull-up (PU) and pull-down (PD) refer to internal input resistors, and are indicated in parentheses.
854S006 Datasheet
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3. Clock Input Function Table
Inputs
Outputs
CLK
nCLK
Q[0:5]
nQ[0:5]
Input-to-Output Mode
0
1
LOW
HIGH
Differential to Differential
1
0
1
Biased[a]
Biased[a]
0
Biased[a]
Biased[a]
0
1
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
[a] Refer to the Application Information section, Wiring the Differential Input to Accept Single-ended Levels.
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
©2017 Integrated Device Technology, Inc.
2
April 11, 2017



Part Number 854S006
Description Differential-to-LVDS Fanout Buffer
Maker Renesas
Total Page 3 Pages
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854S006 Datasheet PDF





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