8A34005 Datasheet | Renesas

Overview The 8A34005 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and Synchronous Ethernet (Sync E) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL). Optional IEEE 1588 software is available under license from Renesas for use with the 8A34005. The software includes clock recovery servos that can be used with the Linux PTP IEEE 1588 protocol stack or with other IEEE 1588 protocol stacks. Typical Applications - Core and access IP switches / routers - Synchronous Ethernet equipment - Tele Boundary Clocks (T-BCs) and Tele Time Slave Clocks (T-TSCs) according to ITU-T G.8273.2 - 10Gb, 40Gb, and 100Gb Ethernet interfaces - Central Office Timing Source and Distribution - Wireless infrastructure for 4.5G and 5G network equipment Features - Four independent timing channels - Each can act as a frequency synthesizer, jitter attenuator, Digitally Controlled Oscillator (DCO), or Digital Phase Lock Loop (DPLL) - DPLLs generate tele pliant clocks - pliant with ITU-T G.8262 for Synchronous Ethernet - pliant with ITU-T G.8262.1 for enhanced Synchronous Ethernet - pliant with legacy SONET/SDH and PDH requirements - DPLL Digital Loop Filters (DLFs) are programmable with cut off frequencies from 0.09m Hz to 12k Hz - DPLL/DCO channels share frequency information using the bo Bus to simplify pliance with ITU-T G.8273.2 - Switching between DPLL and DCO modes is hitless and dynamic - Automatic reference switching between DCO and DPLL modes to simplify support for an external phase/time input interface in a T-BC - Generates output frequencies that are independent of input frequencies via a Fractional Output Divider (FOD) - Each FOD supports output phase tuning with 1ps resolution - 12 Differential / 24 LVCMOS outputs - Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS) - Jitter below...