8A34011 Datasheet | Renesas

Overview The 8A34011 is a port synchronizer for frequency and time/phase for equipment that uses packet-based and physical layer-based equipment synchronization. The 8A34011 is a highly integrated device that provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and Synchronous Ethernet (Sync E) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL). Typical Applications - Core and access IP switches / routers - Synchronous Ethernet equipment - Tele Boundary Clocks (T-BCs) and Tele Time Slave Clocks (T-TSCs) according to ITU-T G.8273.2 - 10Gb, 40Gb, and 100Gb Ethernet interfaces - Central Office Timing Source and Distribution - Wireless infrastructure for 4.5G and 5G network equipment Features - Eight independent timing channels - Each can act as a frequency synthesizer, jitter attenuator, Digitally Controlled Oscillator (DCO), or Digital Phase Lock Loop (DPLL) - DPLL Digital Loop Filters (DLFs) are programmable with cut off frequencies from 17Hz to 22k Hz - Switching between DPLL and DCO modes is hitless and dynamic - Generates output frequencies that are independent of input frequencies via a Fractional Output Divider (FOD) - Each FOD supports output phase tuning with 1ps resolution - 12 Differential / 24 LVCMOS outputs - Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS) - Jitter below 150fs RMS (10k Hz to 20MHz) - LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL output modes supported - Differential output swing is selectable: 400m V / 650m V / 800m V / 910m V - Independent output voltages of 3.3V, 2.5V, or 1.8V - LVCMOS additionally supports 1.5V or 1.2V - The clock phase of each output is individually programmable in 1ns to 2ns steps with a total range of ±180° - 8 differential / 16 single-ended clock inputs - Support frequencies from 1k Hz to 1GHz - Any input can be mapped to any or all of the timing channels -...