900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Renesas Electronics Components Datasheet

8A34012 Datasheet

Port Synchronizer

No Preview Available !

Port Synchronizer for IEEE 1588
Frequency and Time/Phase
8A34012
Datasheet
Overview
The 8A34012 is a port synchronizer for frequency and time/phase
for equipment that uses packet-based and physical layer-based
equipment synchronization.
The 8A34012 is a highly integrated device that provides tools to
manage timing references, clock sources, and timing paths for
IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The
PLL channels can act independently as frequency synthesizers,
jitter attenuators, Digitally Controlled Oscillators (DCO) or Digital
Phase Lock Loops (DPLL).
Typical Applications
Core and access IP switches / routers
Synchronous Ethernet equipment
Telecom Boundary Clocks (T-BCs) and Telecom Time Slave
Clocks (T-TSCs) according to ITU-T G.8273.2
10Gb, 40Gb and 100Gb Ethernet interfaces
Central Office Timing Source and Distribution
Wireless infrastructure for 4.5G and 5G network equipment
Features
Four independent timing channels
Each can act as a frequency synthesizer, jitter attenuator,
Digitally Controlled Oscillator (DCO), or Digital Phase Lock
Loop (DPLL)
DPLL Digital Loop Filters (DLFs) are programmable with
cut-off frequencies from 17Hz to 22kHz
Switching between DPLL and DCO modes is hitless and
dynamic
Generates output frequencies that are independent of input
frequencies via a Fractional Output Divider (FOD)
Each FOD supports output phase tuning with 1ps resolution
8 Differential / 16 LVCMOS outputs
Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)
Jitter below 150fs RMS (10kHz to 20MHz)
LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL
output modes supported
Differential output swing is selectable: 400mV / 650mV /
800mV / 910mV
Independent output voltages of 3.3V, 2.5V, or 1.8V
LVCMOS additionally supports 1.5V or 1.2V
The clock phase of each output is individually programmable
in 1ns to 2ns steps with a total range of ±180°
7 differential / 14 single-ended clock inputs
Support frequencies from 1kHz to 1GHz
Any input can be mapped to any or all of the timing channels
Redundant inputs frequency independent of each other
Any input can be designated as external frame/sync pulse of
EPPS (even pulse per second), 1 PPS (Pulse per Second),
5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz
associated with a selectable reference clock input
Per-input programmable phase offset of up to ±1.638s in
1ps steps
Reference monitors qualify/disqualify references depending on
LOS, activity, frequency monitoring and/or LOS input pins
Loss of Signal (LOS) input pins (via GPIOs) can be assigned
to any input clock reference
Automatic reference selection state machines select the active
reference for each DPLL based on the reference monitors,
priority tables, revertive / non-revertive, and other
programmable settings
System APLL operates from fundamental-mode crystal: 25MHz
to 54MHz or from a crystal oscillator
System DPLL accepts an XO, TCXO, or OCXO operating at
virtually any frequency from 1MHz to 150MHz
DPLLs can be configured as DCOs to synthesize Precision
Time Protocol (PTP) / IEEE 1588 clocks
DCOs generate PTP based clocks with frequency resolution
less than 1.11 × 10-16
DPLL Phase detectors can be used as Time-to-Digital
Converters (TDC) with precision below 1ps
Supports 1MHz I2C or 50MHz SPI serial processor ports
Can configure itself automatically after reset via:
Internal customer definable One-Time Programmable
memory with up to 16 different configurations
Standard external I2C EPROM via separate I2C Master Port
1149.1 JTAG Boundary Scan
10 × 10 mm, 72-QFN package
©2020 Renesas Electronics Corporation
1
August 7, 2020


Renesas Electronics Components Datasheet

8A34012 Datasheet

Port Synchronizer

No Preview Available !

8A34012 Datasheet
Block Diagram
Figure 1. Block Diagram
XO_DPLL
OSCI OSCO
System
DPLL
FOD
Combo Bus
(Frequency Data)
To FODs
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
Reference
Monitors
Reference
Switching
State
Machines
PWM
Decoders
DPLL /
DCO_0
FOD
DPLL /
DCO_1
FOD
DPLL /
DCO_2
FOD
CLK6
Status and Configuration
Re gist er s
DPLL /
DCO_3
FOD
OTP
Osc
System
APLL
Div
Q0
Div
Q1
Div
Q2
Div
Q3
Div
Q4
Div
Q5
Div
Q6
Div
Q7
I2C Master
SPI/I2C
PWM Encoders GPIO / JTAG
Description
The 8A34012 is a port synchronizer for frequency and time/phase for equipment that uses packet based and physical layer based
equipment synchronization. The 8A34011 is a highly integrated device that provides tools to manage timing references, clock sources
and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency
synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL).
The 8A34012 supports multiple independent timing paths that can each be configured as a DPLL or as a DCO. Input-to-input,
input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly
synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, and 10GBASE-W and lower-rate Ethernet interfaces; as well
as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).
The internal System APLL must be supplied with a low phase noise reference clock with frequency between 25MHz and 54MHz. The
output of the System APLL is used for clock synthesis by all of the Fractional Output Dividers (FODs) in the device. The System APLL
reference can come from an external crystal oscillator connected to the OSCI pin or from an internal oscillator that uses a crystal
connected between the OSCI and OSCO pins.
©2020 Renesas Electronics Corporation
2
August 7, 2020



Part Number 8A34012
Description Port Synchronizer
Maker Renesas
Total Page 3 Pages
PDF Download

8A34012 Datasheet PDF





Similar Datasheet

1 8A34012 Port Synchronizer
Renesas





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy