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8S89833 - 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination

Description

The 8S89833 is a high speed 1-to-4 Differential-to-LVDS Fanout Buffer with Internal Termination.

The 8S89833 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel.

Features

  • Four differential LVDS outputs.
  • IN, nIN input pair can accept the following differential input levels: LVPECL, LVDS, CML.
  • Output frequency: 2GHz.
  • Cycle-to-cycle jitter, RMS: 3.5ps (maximum).
  • Additive phase jitter, RMS: 0.03ps (typical).
  • Output skew: 30ps (maximum).
  • Part-to-part skew: 200ps (maximum).
  • Propagation Delay: 600ps (maximum).
  • Full 3.3V supply mode.
  • -40°C to 85°C ambient operating temperature.

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Datasheet preview – 8S89833

Datasheet Details

Part number 8S89833
Manufacturer Renesas
File Size 632.39 KB
Description 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination
Datasheet download datasheet 8S89833 Datasheet
Additional preview pages of the 8S89833 datasheet.

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Full PDF Text Transcription

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Low Skew, 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination 8S89833 Datasheet Description The 8S89833 is a high speed 1-to-4 Differential-to-LVDS Fanout Buffer with Internal Termination. The 8S89833 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, and CML to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes.
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