8T74S208B - LVDS Clock Divider and Fanout Buffer

Renesas

Datasheet Details

Part number	8T74S208B
Manufacturer	Renesas ↗
File Size	632.27 KB
Description	LVDS Clock Divider and Fanout Buffer
Datasheet	8T74S208B-Renesas.pdf

The 8T74S208B is a high-performance differential LVDS clock divider and fanout buffer.

One differential input reference clock.
Differential pair can accept the following differential input levels: LVDS, LVPECL, CML.
Integrated input termination resistors.
Eight LVDS outputs.
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8.
Maximum input clock frequency: 1GHz.
LVCMOS interface levels for the control inputs.
Individual output enabled/ disabled by I2C interface.
Output skew: 45ps (maximum).

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Published: Jun 4, 2020 |