Description
The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1.
12-output PCIe Gen3 zero-delay/fanout buffer
Output
Features
- Twelve 0.7V current mode differential HSCL output pairs
Features.
- 3 selectable SMBus addresses; multiple devices can share the same SMBus segment.
- 12 OE# pins; hardware control of each output.
- PLL or bypass mode; PLL can dejitter incoming clock.
- Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLLs.
- Spread spectrum compatible; tracks spreading input clock for
low EMI.
- SMBus interface; unused outputs can be disabled.
- Undriven differential.
9DB1233-Renesas.pdf
