9DB1233 Datasheet | IDT

Twelve Output Differential Buffer for PCIe Gen3 Remended Application 12 output PCIe Gen3 zero-delay/fanout buffer General Description The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards patible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. Output Features - 12 - 0.7V current mode differential HCSL output pairs Features /Benefits - 3 Selectable SMBus Addresses/Mulitple devices can...