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9DB1233 Datasheet Twelve Output Differential Buffer

Manufacturer: IDT

Overview: Twelve Output Differential Buffer for PCIe Gen3 DATASHEET 9DB1233 Recommended Application 12 output PCIe Gen3 zero-delay/fanout.

Datasheet Details

Part number 9DB1233
Manufacturer IDT
File Size 182.17 KB
Description Twelve Output Differential Buffer
Datasheet 9DB1233-IDT.pdf

General Description

The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1.

The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator.

It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking.

Key Features

  • 12 - 0.7V current mode differential HCSL output pairs Features/Benefits.
  • 3 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment.
  • 12 OE# pins/Hardware control of each output.
  • PLL or bypass mode/PLL can dejitter incoming clock.
  • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's.
  • Spread Spectrum Compatible/tracks spreading input clock for low EMI.
  • SMBus Interface/unu.

9DB1233 Distributor