Datasheet Details
| Part number | 9DB1233 |
|---|---|
| Manufacturer | Renesas |
| File Size | 490.18 KB |
| Description | 12-Output Differential Buffer |
| Datasheet |
 9DB1233 Datasheet
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General Description
The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1.
The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator.
Key Features
- Twelve 0.7V current mode differential HSCL output pairs Features.
- 3 selectable SMBus addresses; multiple devices can share the same SMBus segment.
- 12 OE# pins; hardware control of each output.
- PLL or bypass mode; PLL can dejitter incoming clock.
- Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs.
- Spread spectrum compatible; tracks spreading input clock for low EMI.
- SMBus interface; unused outputs can be disabled.
- Undriven differential.