9FGL0241 Key Features
- 2, 4, 6, or 8 100MHz PCIe output pairs
- One 3.3V LVCMOS REF output with Wake-On-LAN (WOL)
- See AN-891 for easy AC-coupling to other logic families
- 90fs RMS typical jitter (PCIe Gen5 CC)
- < 50ps cycle-to-cycle jitter on differential outputs
- < 50ps output-to-output skew on differential outputs
- ±0ppm synthesis error on differential outputs
- Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
- 112-206 mW typical power consumption (at 3.3V)
- VDDIO rail allows 35% power savings at optional 1.05V
