HD74ACT112 - Dual JK Negative Edge-Triggered Flip-Flop

This page provides the datasheet information for the HD74ACT112, a member of the HD74AC112 Dual JK Negative Edge-Triggered Flip-Flop family.

Product Overview

Renesas

Part number	HD74ACT112
Manufacturer	Renesas
File Size	209.33 KB
Description	Dual JK Negative Edge-Triggered Flip-Flop
Datasheet	HD74ACT112 Datasheet
Additional preview pages of the HD74ACT112 datasheet.

The HD74AC112/HD74ACT112

individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Features.
Outputs Source/Sink 24 mA.
HD74ACT112 has TTL-Comp.

HD74ACT112 - Dual JK Negative Edge-Triggered Flip-Flop (Hitachi Semiconductor)
HD74ACT107 - Dual JK Flip-Flop (with Separate Clear and Clock) (Hitachi Semiconductor)
HD74ACT125 - Quad Buffer/Line Driver with 3-State Output (Hitachi Semiconductor)
HD74ACT126 - Quad Buffer/Line Driver with 3-State Output (Hitachi Semiconductor)
HD74ACT138 - 1-of-8 Decoder/Demultiplexer (Hitachi Semiconductor)
HD74ACT139 - Dual 1-of-4 Decoder/Demultiplexer (Hitachi Semiconductor)
HD74ACT161 - Synchronous Presettable Binary Counter (Hitachi Semiconductor)
HD74ACT163 - Synchronous Presettable Binary Counter (Hitachi Semiconductor)
HD74ACT164 - Serial-In/ Parallel-Out Shift Register (Hitachi Semiconductor)
HD74ACT165 - Parallel-Load 8-bit Shift Register (Hitachi Semiconductor)

Other Datasheets by Renesas

Published: Dec 4, 2017 |