HD74ACT112 Datasheet
Dual JK Negative Edge-Triggered Flip-Flop
Manufacturer: Renesas
Download the HD74ACT112 datasheet PDF.
This datasheet also includes the HD74AC112 variant, as both parts are published together in a single manufacturer document.
individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Features.
HD74ACT112 Datasheet
