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HD74HC377
Octal D-type Flip-Flops (with Enable)
REJ03D0622-0200 (Previous ADE-205-501)
Rev.2.00 Mar 30, 2006
Description
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G input.