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HD74LS191P - Synchronous Up / Down 4-bit Binary Counter

Download the HD74LS191P datasheet PDF. This datasheet also covers the HD74LS191 variant, as both devices belong to the same synchronous up / down 4-bit binary counter family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS191P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74LS191FPEL SOP-16 pin (JEITA) PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity).
  • EL (2,000 pcs/reel) Rev.2.00, Feb.18.2005, page 1 of 10 HD74LS191 Pin Arrangement Data B Input 1 Outputs QB 2 QA 3 Enable G 4 Inputs Down/Up 5 Outputs.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74LS191-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74LS191P
Manufacturer Renesas
File Size 263.97 KB
Description Synchronous Up / Down 4-bit Binary Counter
Datasheet download datasheet HD74LS191P Datasheet

📁 Similar Datasheet

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HD74LS193 Synchronous Up/Down 4-bit Binary Counters Hitachi Semiconductor
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Other Datasheets by Renesas

Part Number Description
HD74LS191 Synchronous Up / Down 4-bit Binary Counter
HD74LS190 Synchronous Up / Down Decade Counter
HD74LS190P Synchronous Up / Down Decade Counter
HD74LS192 Synchronous Up / Down Decade Counter
HD74LS192P Synchronous Up / Down Decade Counter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HD74LS191 Synchronous Up / Down 4-bit Binary Counter (single clock line) REJ03D0453–0200 Rev.2.00 Feb.18.2005 Synchronous operation is provided by having all flip-flops clocked simultaneously so that the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a low-to-high-level transition of the clock input if the enable input is high. The direction of the count is determined by the level of the down / up input. When low, the counter counts up and when high, it counts down. Level changes at the down / up input should be made only when the clock input is high.