ICS663 Datasheet - Renesas

PLL BUILDING BLOCK

ICS663 Features

* please refer to the ICS673-01. Features

* Packaged in 8-pin SOIC (Pb free)

* Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to 120 MHz (5 V)

* External PLL loop filter enables configuration for a wide range of input frequencies

* Ability to accept an input clock

ICS663 General Description

The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented with the ICS674-0.

ICS663 Datasheet (352.97 KB)