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ICS8516I - Clock Distribution

General Description

Perfor mance Clock Solutions from IDT.

Key Features

  • Sixteen Differential LVDS outputs.
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
  • Maximum output frequency: 700MHz.
  • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks.
  • Translates any single-ended input signal to LVDS with resistor bias on nCLK input.
  • Multiple output enable inputs for disabling unused outputs in reduced fanout.

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Datasheet Details

Part number ICS8516I
Manufacturer Renesas
File Size 564.22 KB
Description Clock Distribution
Datasheet download datasheet ICS8516I Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Low Skew, 1-to-16 Differential-toLVDS, Clock Distribution Chip ICS8516I DATA SHEET GENERAL DESCRIPTION The ICS8516I is a low skew, high performance 1- ICS to-16 Differential-to-LVDS Clock Distribution Chip HiPerClockS™ and a member of the HiPerClockS™ family of High Perfor mance Clock Solutions from IDT. The ICS8516I CLK, nCLK pair can accept any differ- ential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS8516I provides a low power, low noise, point-to-point solu- tion for distributing clock signals over controlled impedances of 100Ω. Dual output enable inputs allow the ICS8516I to be used in a 1-to-16 or 1-to-8 input/output mode.