900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Renesas Electronics Components Datasheet

ICS8516I Datasheet

Clock Distribution

No Preview Available !

Low Skew, 1-to-16 Differential-to-
LVDS, Clock Distribution Chip
ICS8516I
DATA SHEET
GENERAL DESCRIPTION
The ICS8516I is a low skew, high performance 1-
ICS
to-16 Differential-to-LVDS Clock Distribution Chip
HiPerClockS™ and a member of the HiPerClockS™ family of High
Perfor mance Clock Solutions from IDT. The
ICS8516I CLK, nCLK pair can accept any differ-
ential input levels and translates them to 3.3V LVDS output
levels. Utilizing Low Voltage Differential Signaling (LVDS), the
ICS8516I provides a low power, low noise, point-to-point solu-
tion for distributing clock signals over controlled impedances
of 100Ω.
Dual output enable inputs allow the ICS8516I to be used in a
1-to-16 or 1-to-8 input/output mode. Guaranteed output and
part-to-part skew specifications make the ICS8516I ideal for
those applications demanding well defined performance and
repeatability.
FEATURES
Sixteen Differential LVDS outputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 700MHz
Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
Translates any single-ended input signal to LVDS
with resistor bias on nCLK input
Multiple output enable inputs for disabling unused
outputs in reduced fanout applications
LVDS compatible
Output skew: 65ps (maximum)
Part-to-part skew: 550ps (maximum)
Propagation delay: 2.4ns (maximum)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
CLK
nCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
OE1
OE2
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
PIN ASSIGNMENT
VDD
nQ5
Q5
nQ4
Q4
VDD
GND
nQ3
Q3
nQ2
Q2
VDD
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
ICS8516I
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
VDD
nQ10
Q10
nQ11
Q11
VDD
GND
nQ12
Q12
nQ13
Q13
VDD
48-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
ICS8516I REVISION B SEPTEMBER 10, 2009
1
©2009 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

ICS8516I Datasheet

Clock Distribution

No Preview Available !

ICS8516I Data Sheet
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 1. PIN DESCRIPTIONS
Number
1, 6, 12,
25, 31, 36
Name
V
DD
Type
Power
Description
Positive supply pins.
2, 3
nQ5, Q5
Output
Differential output pair. LVDS interface levels.
4, 5
7, 17, 20,
30, 41, 44
nQ4, Q4
GND
Output
Power
Differential output pair. LVDS interface levels.
Power supply ground.
8, 9
nQ3, Q3
Output
Differential output pair. LVDS interface levels.
10, 11
nQ2, Q2 Output
Differential output pair. LVDS interface levels.
13, 14
nQ1, Q1 Output
Differential output pair. LVDS interface levels.
15, 16
nQ0, Q0
Output
Differential output pair. LVDS interface levels.
18
nCLK
Input
Pullup Inverting differential clock input.
19
CLK
Input Pulldown Non-inverting differential clock input.
21, 22
Q15, nQ15 Output
Differential output pair. LVDS interface levels.
23, 24
Q14, nQ14 Output
Differential output pair. LVDS interface levels.
26, 27
Q13, nQ13 Output
Differential output pair. LVDS interface levels.
28, 29
Q12, nQ12 Output
Differential output pair. LVDS interface levels.
32, 33
Q11, nQ11 Output
Differential output pair. LVDS interface levels.
34, 35
Q10, nQ10 Output
Differential output pair. LVDS interface levels.
37, 38
Q9, nQ9
Output
Differential output pair. LVDS interface levels.
39, 40
Q8, nQ8
Output
Differential output pair. LVDS interface levels.
42, 43
45, 46
OE2, OE1
nQ7, Q7
Input
Output
Pullup
Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15;
OE1 controls outputs Q0, nQ0 thru Q7, nQ7.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
47, 48
nQ6, Q6
Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS8516I REVISION B SEPTEMBER 10, 2009
2
©2009 Integrated Device Technology, Inc.



Part Number ICS8516I
Description Clock Distribution
Maker Renesas
Total Page 3 Pages
PDF Download

ICS8516I Datasheet PDF





Similar Datasheet

1 ICS8516 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION
Integrated Circuit Systems
2 ICS8516I Clock Distribution
Renesas
3 ICS8516I 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION
Integrated Circuit Systems





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy