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ICS8516 - 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION

General Description

The ICS8516 is a low skew, high performance 1-to-16 Differential-to-LVDS Clock Distribution HiPerClockS™ Chip and a member of the HiPerClock S ™ family of High Performance Clock Solutions from ICS.

Key Features

  • Sixteen differential LVDS outputs.
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
  • Maximum output frequency: 700MHz.
  • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks.
  • Translates any single-ended input signal to LVDS with resistor bias on nCLK input.
  • Multiple output enable inputs for disabling unused outputs in reduced fanout.

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Datasheet Details

Part number ICS8516
Manufacturer Integrated Circuit Systems
File Size 204.09 KB
Description 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION
Datasheet download datasheet ICS8516 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Integrated Circuit Systems, Inc. ICS8516 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP FEATURES • Sixteen differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks • Translates any single-ended input signal to LVDS with resistor bias on nCLK input • Multiple output enable inputs for disabling unused outputs in reduced fanout applications • LVDS compatible • Output skew: 90ps (maximum) • Part-to-part skew: 500ps (maximum) • Propagation delay: 2.4ns (maximum) • Additive phase jitter, RMS: 148fs (typical) • 3.