Description
Perfor mance Clock Solutions from IDT.
Features
- Sixteen Differential LVDS outputs.
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
- Maximum output frequency: 700MHz.
- Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks.
- Translates any single-ended input signal to LVDS with resistor bias on nCLK input.
- Multiple output enable inputs for disabling unused outputs in reduced fanout.
ICS8516I Datasheet
