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ICS85214I Datasheet

Differential-to-HSTL Fanout Buffer

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Low Skew, 1-to-5, Differential-to-HSTL
Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
ICS85214I
DATA SHEET
GENERAL DESCRIPTION
The ICS85214I is a low skew, high performance 1-to-5 Differen-
tial-to-HSTL Fanout Buffer.The CLK0, nCLK0 pair can accept most
standard differential input levels. The single ended CLK1 input ac-
cepts LVCMOS or LVTTL input levels. Guaranteed output and part
to part skew characteristics make the ICS85214I ideal for those
clock distribution applications demanding well defined performance
and repeatability.
FEATURES
Five differential HSTL compatible outputs
Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL
clock inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Output frequency up to 700MHz
Translates any single ended input signal to HSTL levels
with resistor bias on nCLK0 input
Output skew: 40ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 1.8ns (maximum)
3.3V core, 1.8V output operating supply
Available in Lead-Free (RoHS 6) package
-40°C to 85°C ambient operating temperature
For functional replacement part use 8523
BLOCK DIAGRAM
PIN ASSIGNMENT
ICS8521AGI REVISION B JUNE 3, 2016
ICS85214I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
1


Renesas Electronics Components Datasheet

ICS85214I Datasheet

Differential-to-HSTL Fanout Buffer

No Preview Available !

ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1, 2 Q0, nQ0 Output
Differential output pair. HSTL interface levels.
3, 4 Q1, nQ1 Output
Differential output pair. HSTL interface levels.
5, 6 Q2, nQ2 Output
Differential output pair. HSTL interface levels.
7, 8 Q3, nQ3 Output
Differential output pair. HSTL interface levels.
9, 10
Q4, nQ4 Output
Differential output pair. HSTL interface levels.
11
GND
Power
Power supply ground.
12
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0, nCLK0 input. LVTTL / LVCMOS interface levels.
13, 17
nc Unused
No connect.
14
nCLK0
Input Pullup Inverting differential clock input.
15
CLK0
Input Pulldown Non-inverting differential clock input.
16
CLK1
Input Pulldown Clock input. LVTTL / LVCMOS interface levels.
18 V Power
DD
Power supply pin.
Synchronizing clock enable. When LOW, clock outputs follow clock input.
19 nCLK_EN Input Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
20 V
Power
DDO
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
ICS85214AGI REVISION B JUNE 3, 2016
2


Part Number ICS85214I
Description Differential-to-HSTL Fanout Buffer
Maker Renesas
Total Page 17 Pages
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