ICS854S296I-33 Datasheet LVDS Programmable Delay-Line

Manufacturer: Renesas

Datasheet Details

Part number	ICS854S296I-33
Manufacturer	Renesas
File Size	420.46 KB
Description	LVDS Programmable Delay-Line
Download	ICS854S296I-33 Download (PDF)

The ICS854S296I-33 is a high performance LVDS Programmable Delay Line.

The delay can vary from 2.2ns to 12.5ns in 10ps steps.

The ICS854S296I-33 is characterized to operate from a 3.3V power supply and is guaranteed over industrial temperature range.

FemtoClock® LVDS Programmable Delay Line ICS854S296I-33 DATA SHEET.

One LVDS level output.
One differential clock input pair.
Differential input clock (IN, nIN) can accept the following signaling levels: LVPECL, LVDS, CML.
Maximum frequency: 1.2GHz.
Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps.
D[9:0] can accept LVPECL, LVCMOS or LVTTL levels.
Full 3.3V supply voltages.
-40°C to 85°C ambient operating temperature.
Available in lead-free (RoHS 6) package ICS854S296DKI-33.

Part Number	Description
ICS854S202I-01	Differential-To-LVDS Multiplexer
ICS854S01I	2:1 Differential-to-LVDS Multiplexer
ICS854S054I	4:1 Differential-to-LVDS Clock Multiplexer
ICS854S058I	8:1 Differential-to-LVDS Clock Multiplexer
ICS854S54I-01	Differential-to-LVDS Multiplexer
ICS854104	Differential-to-LVDS Fanout Buffer
ICS8543	Differential-to-LVDS Fanout Buffer
ICS8543I	Differential-to-LVDS Fanout Buffer
ICS8545-02	1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
ICS8546-01	Crystal-to-LVDS Fanout Buffer