900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Renesas Electronics Components Datasheet

ICS9250-28 Datasheet

Frequency Generator & Integrated Buffer

No Preview Available !

ICS9250-28
Frequency Generator & Integrated Buffers for Celeron & PII/III
Recommended Application:
810/810E and 815 type chipset.
Output Features:
• 2 CPU (2.5V) (up to 133MHz achievable through I2C)
• 13 SDRAM (3.3V) (up to 133MHz achievable
through I2C)
• 2 PCI (3.3 V) @33.3MHz
• 1 IOAPIC (2.5V) @ 33.3 MHz
• 3 Hublink clocks (3.3 V) @ 66.6 MHz
• 2 (3.3V) @ 48 MHz (Non spread spectrum)
• 1 REF (3.3V) @ 14.318 MHz
Features:
• Supports spread spectrum modulation,
0 to -0.5% down spread.
• I2C support for power management
• Efficient power management scheme through PD#
• Uses external 14.138 MHz crystal
• Alternate frequency selections available through I2C
control.
Pin Configuration
IOAPIC
1
VDDL
2
GND
3
*FS1/REF0
4
VDDREF
5
X1
6
X2
7
GND
8
VDD3V66
9
3V66_0
10
3V66_1
11
3V66_2
12
GND
13
VDDPCI
14
PCICLK0
15
PCICLK1
16
GND
17
FS0
18
GND
19
VDDA
20
PD#
21
SCLK
22
SDATA
23
GND
24
VDD48
25
48MHz_0
26
48MHz_1
27
FS2
28
56
VDDL
55
GND
54
CPUCLK0
53
CPUCLK1
52
GND
51
SDRAM0
50
SDRAM1
49
VDDSDR
48
GND
47
SDRAM2
46
SDRAM3
45
SDRAM4
44
VDDSDR
43
GND
42
SDRAM5
41
SDRAM6
40
VDDSDR
39
GND
38
SDRAM7
37
SDRAM8
36
SDRAM9
35
VDDSDR
34
GND
33
SDRAM10
32
SDRAM11
31
VDDSDR
30
GND
29
SDRAM12
56-Pin 300mil SSOP
* This input has a 50KW pull-down to GND.
Block Diagram
X1
XTAL
X2
OSC
PLL1
Spread
Spectrum
/2 /3
FS(2:0)
PD#
SDATA
SCLK
Control
Logic
Config
Reg
PLL2
/2
/2
Functionality
FS2 FS0 FS1
Function
0
0
X Tristate
0
1
X Test
REF0
1
0
0
Active CPU = 66MHz
SDRAM = 100MHz
1
1
0
Active CPU = 100MHz
SDRAM = 100MHz
2 CPU66/100/133 [1:0]
1
0
1
Active CPU = 133MHz
SDRAM = 133MHz
3V66 (2:0)
3
SDRAM (12:0)
13
1
1
1
Active CPU = 133MHz
SDRAM = 100MHz
PCICLK (1:0)
2
IOAPIC
2 48MHz (1:0)
Power Groups
Analog
VDDREF = X1, X2
VDDA = PLL1
VDD48 = PLL2
Digital
VDD3V66, VDDPCI
VDDSDR, VDDL
Third party brands and names are the property of their respective owners.


Renesas Electronics Components Datasheet

ICS9250-28 Datasheet

Frequency Generator & Integrated Buffer

No Preview Available !

ICS9250-28
General Description
The ICS9250-28 is part of a two chip clock solution for 810/810E and 815 type chipset. Combined with the
ICS9112-17, the ICS9250-28 provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS9250-28 employs a proprietary closed loop design, which tightly controls the percentage of spreading over
process and temperature variations.
Pin Configuration
PIN NUMBER PIN NAME
1
IOAPIC
2, 56
VDDL
FS1
4
REF0
5, 9, 14, 20, 25,
31, 35, 40, 44, 49
VDD
6
X1
7
X2
3, 8, 13, 17, 19,
24, 30, 34, 39, GND
43, 48, 52, 55
12, 11, 10 3V66 (2:0)
28, 18
FS (2, 0)
16, 15
PCICLK[1:0]
21
PD#
22
SCLK
TYPE
DESCRIPTION
OUT 2.5V clock output running at 33.3MHz.
PWR 2.5V power supply for CPU & IOAPIC
IN Function Select pin. Determines CPU frequency, all output functionality
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply
IN
OUT
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply
OUT 3.3V Fixed 66MHz clock outputs for HUB
IN
Function Select pins. Determines CPU frequency, all output functionality.
Please refer to Functionality table on page 3.
OUT 3.3V PCI clock outputs
Asynchronous active low input pin used to power down the device into
IN
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
IN Clock pin of I2C circuitry 5V tolerant
23
SDATA
I/O Data pin for I2C circuitry 5V tolerant
26, 27
48MHz_0
29, 32, 33, 36,
37, 38, 41, 42,
45, 46, 47, 50, 51
SDRAM
(12:0)
54, 53
CPUCLK (1:0)
OUT 3.3V Fixed 48MHz clock outputs.
OUT
OUT
3.3V output running 100MHz. All SDRAM outputs can be turned off
through I2C
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS (2:0) pins.
2


Part Number ICS9250-28
Description Frequency Generator & Integrated Buffer
Maker Renesas
PDF Download

ICS9250-28 Datasheet PDF






Similar Datasheet

1 ICS9250-22 Frequency Generator & Integrated Buffers
Integrated Circuit Systems
2 ICS9250-23 Frequency Generator & Integrated Buffers
Integrated Circuit Systems
3 ICS9250-25 Frequency Generator & Integrated Buffers
Integrated Circuit Systems
4 ICS9250-26 Frequency Generator & Integrated Buffers
Integrated Circuit Systems
5 ICS9250-27 Frequency Generator & Integrated Buffers
Integrated Circuit Systems
6 ICS9250-28 Frequency Generator & Integrated Buffers
Integrated Circuit Systems
7 ICS9250-28 Frequency Generator & Integrated Buffer
Renesas
8 ICS9250-29 Frequency Generator & Integrated Buffers
Integrated Circuit Systems





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy