ICS93705 Datasheet - Renesas

DDR Phase Lock Loop Zero Delay Clock Buffer

* Low skew, low jitter PLL clock driver

* I2C for functional and output control

* Feedback pins for input to output synchronization

* Spread Spectrum tolerant inputs

* 3.3V tolerant CLK_INT input Switching Characteristics:

* PEAK - PEAK jitter (66MHz)

ICS93705

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Ddr phase lock loop zero delay clock buffer.

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ICS93705 DDR Phase Lock Loop Zero Delay Clock Buffer Renesas

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