Datasheet Details
| Part number | ICS97U8770 |
|---|---|
| Manufacturer | Renesas |
| File Size | 1.91 MB |
| Description | 1.8V Wide Range Frequency Clock Driver |
| Datasheet | ICS97U8770-Renesas.pdf |
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Overview: ICS97U870 Advance Information Pin.
| Part number | ICS97U8770 |
|---|---|
| Manufacturer | Renesas |
| File Size | 1.91 MB |
| Description | 1.8V Wide Range Frequency Clock Driver |
| Datasheet | ICS97U8770-Renesas.pdf |
|
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s Terminal Name AGND AVDD CLK_INT CLK_INC FB_INT FB_INC FB_OUTT FB_OUTC Description Analog Ground Analog power Clock input with a (10K-100K Ohm) pulldown resistor Complentary clock input with a (10K-100K Ohm) pulldown resistor Feedback clock input Complementary feedback clock input Feedback clock output Complementary feedback clock output OE OS GND VDDQ CLKT[0:9] CLKC[0:9] NB Output Enable (Asynchronous) Output Select (tied to GND or V000) Ground Logic and output power Clock outputs Complementary clock outputs No ball Electrical Characteristics Ground 1.8 V nominal Differential input Differential input Differential input Differential input Differential output Differential output LVCMOS input LVCMOS input Ground 1.8V nominal Differential outputs Differential outputs The PLL clock buffer, ICS97U870, is designed for aVooa of 1.8 V, a AVoo of 1.8V and differential data input and output levels.
Package options include a plastic 52-ballVFBGA and a 40-pin MLF.
ICS97U870 is a zero delay buffer that distributes a differential clock input pair(CLK_INT, CLK_INC) to ten differential pair of clock outputs(CLKT[0:9], CLKC[0:91) and one differential pair feedback clock outputs(FB_OUTT, FBOUTC).
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