* Differential clock signal
* Meets SSTL_2 signal data
* Supports SSTL_2 class I & II specifications
* Low-voltage operation - Voo = 2.3V to2.7V
* 48 pin TSS OP and TVS OP package Truth Table1 Inputs RESET# CLK CLK# L Xor Xor Floating Floating H t J,
ICSSSTVF16857 Datasheet (484.89 KB)
ICSSSTVF16857
484.89 KB
Ddr 14-bit registered buffer.
ENESAS ICSSSTVF16857 Advance Information DDR 14-Bit Registered Buffer Recommended Applications: DDR Memory Modules Provide.
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