Datasheet4U Logo Datasheet4U.com

ICSSSTVF16857 - DDR 14-Bit Registered Buffer

Key Features

  • Differential clock signal.
  • Meets SSTL_2 signal data.
  • Supports SSTL_2 class I & II specifications.
  • Low-voltage operation - Voo = 2.3V to2.7V.
  • 48 pin TSS OP and TVS OP package Truth Table1 Inputs RESET# CLK CLK# L Xor Xor Floating Floating H t J, H t J, H LorH LorH D Xor Floating H L X Q Outputs Q L H L QlZ> Pin Configuration Q1 1 48 D1 Q2 2 47 D2 GND 3 46 GND VDDQ 4 45 VDD QJ 5 44 DJ Q4 6 43 D4 Q5 7 42 D5 ->cc:ooGND VDDQ.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICSSSTVF16859 DDR 13-Bit to 26-Bit Registered Buffer Integrated Circuit Systems
ICSSSTV16857 DDR 14-Bit Registered Buffer Integrated Circuit Systems
ICSSSTV16859 DDR 13-Bit to 26-Bit Registered Buffer Integrated Circuit Systems
ICSSSTV32852 DDR 24-Bit to 48-Bit Registered Buffer Integrated Circuit Systems
ICSSSTVA16857 DDR 14-Bit Registered Buffer Integrated Circuit Systems

Other Datasheets by Renesas

Part Number Description
ICSSSTVA16859C DDR 13-Bit to 26-Bit Registered Buffer
ICS1493-17 CLOCK SYNTHESIZER
ICS180-01 LOW EMI CLOCK GENERATOR
ICS180-51 LOW EMI CLOCK GENERATOR
ICS181-01 LOW EMI CLOCK GENERATOR

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
�ENESAS ICSSSTVF16857 Advance Information DDR 14-Bit Registered Buffer Recommended Applications: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • Low-voltage operation - Voo = 2.3V to2.7V • 48 pin TSS OP and TVS OP package Truth Table1 Inputs RESET# CLK CLK# L Xor Xor Floating Floating H t J, H t J, H LorH LorH D Xor Floating H L X Q Outputs Q L H L QlZ> Pin Configuration Q1 1 48 D1 Q2 2 47 D2 GND 3 46 GND VDDQ 4 45 VDD QJ 5 44 DJ Q4 6 43 D4 Q5 7 42 D5 ->cc:ooGND VDDQ 8 9 t-- It) 41 D6 40 D7 Q6 10 39 CU<# Q7 VDDQ 11 12 LL.