ICSSSTVF16857 - DDR 14-Bit Registered Buffer

Renesas

Datasheet Details

Differential clock signal.
Meets SSTL_2 signal data.
Supports SSTL_2 class I & II specifications.
Low-voltage operation - Voo = 2.3V to2.7V.
48 pin TSS OP and TVS OP package Truth Table1 Inputs RESET# CLK CLK# L Xor Xor Floating Floating H t J, H t J, H LorH LorH D Xor Floating H L X Q Outputs Q L H L QlZ> Pin Configuration Q1 1 48 D1 Q2 2 47 D2 GND 3 46 GND VDDQ 4 45 VDD QJ 5 44 DJ Q4 6 43 D4 Q5 7 42 D5 ->cc:ooGND VDDQ.

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Published: Jun 4, 2020 |