IDT2305A
FEATURES
:
- Phase-Lock Loop Clock Distribution
- 10MHz to 133MHz operating frequency
- Distributes one clock input to one bank of five outputs
- Zero Input-Output Delay
- Output Skew < 250ps
- Low jitter <200 ps cycle-to-cycle
- IDT2305A-1 for Standard Drive
- IDT2305A-1H for High Drive
- No external RC network required
- Operates at 3.3V VDD
- Power down mode
- Available in SOIC package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
:
The IDT2305A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the ining clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2305A is an 8-pin version of the IDT2309A. IDT2305A accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF...
