Download IDT72285 Datasheet PDF
IDT72285 datasheet preview
IDT72285 page 2
Page 2
IDT72285 page 3
Page 3

IDT72285 Key Features

  • Independent Read and Write Clocks (permit reading and writing
  • Choose among the following memory organizations: IDT72275
  • 32,768 x 18 IDT72285
  • 65,536 x 18
  • Pin-patible with the IDT72255LA/72265LA SuperSync FIFOs
  • 10ns read/write cycle time (6.5ns access time)
  • Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64
  • High-performance submicron CMOS technology
  • Industrial temperature range (-40°C to +85°C) is available
  • Fixed, low first word data latency time

Other IDT72285 Datasheets

Manufacturer Part Number Description
IDT Logo IDT IDT72285 (IDT72275 / IDT72285) CMOS SUPERSYNC FIFO

View all IDT72285 datasheets →

IDT72285 Description

Master Reset clears entire FIFO The IDT72275/72285 are exceptionally deep, high speed, CMOS First-In- Partial Reset clears data, but retains programmable settings Retransmit operation with fixed, low first word data T R latency time Empty, Full and Half-Full flags signal FIFO status R O Programmable Almost-Empty and Almost-Full flags, each flag F can default to one of two preselected offsets A Program partial flags...