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NP60N04MUG Datasheet

N-CHANNEL POWER MOS FET

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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP60N04MUG
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
The NP60N04MUG is N-channel MOS Field Effect Transistor designed for high current switching applications.
ORDERING INFORMATION
PART NUMBER
LEAD PLATING
PACKING
NP60N04MUG-S18-AY Note
Pure Sn (Tin)
Tube 50 p/tube
Note Pb-free (This product does not contain Pb in the external electrode).
PACKAGE
TO-220 (MP-25K) typ. 1.9 g
FEATURES
Super low on-state resistance
RDS(on) = 6.3 mΩ MAX. (VGS = 10 V, ID = 30 A)
Channel temperature 175 degree rated
(TO-220)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
Gate to Source Voltage (VDS = 0 V)
VGSS
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
ID(DC)
ID(pulse)
Total Power Dissipation (TC = 25°C)
PT1
Total Power Dissipation (TA = 25°C)
PT2
Channel Temperature
Tch
Storage Temperature
Repetitive Avalanche Current Note2
Repetitive Avalanche Energy Note2
Tstg
IAR
EAR
40
±20
±60
±240
88
1.8
175
55 to +175
30
90
V
V
A
A
W
W
°C
°C
A
mJ
Notes 1. PW 10 μs, Duty Cycle 1%
2. Tch 150°C, VDD = 20 V, RG = 25 Ω, VGS = 20 0 V, L = 100 μH
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
1.70
83.3
°C/W
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D18663EJ2V0DS00 (2nd edition)
Date Published April 2007 NS CP(K)
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2007


Renesas Electronics Components Datasheet

NP60N04MUG Datasheet

N-CHANNEL POWER MOS FET

No Preview Available !

NP60N04MUG
<R>
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS VDS = 40 V, VGS = 0 V
Gate Leakage Current
IGSS VGS = ±20 V, VDS = 0 V
Gate to Source Threshold Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(th)
| yfs |
RDS(on)
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 30 A
VGS = 10 V, ID = 30 A
Input Capacitance
Ciss VDS = 25 V,
Output Capacitance
Coss
VGS = 0 V,
Reverse Transfer Capacitance
Crss f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 20 V, ID = 30 A,
Rise Time
tr VGS = 10 V,
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
tf
Total Gate Charge
QG VDD = 32 V,
Gate to Source Charge
QGS VGS = 10 V,
Gate to Drain Charge
Body Diode Forward Voltage Note
QGD
VF(S-D)
ID = 60 A
IF = 60 A, VGS = 0 V
Reverse Recovery Time
trr IF = 60 A, VGS = 0 V,
Reverse Recovery Charge
Note Pulsed
Qrr di/dt = 100 A/μs
MIN.
2.0
19
TYP.
38
5.0
3200
320
210
21
10
48
10
60
15
21
0.95
33
40
MAX.
1
±100
4.0
6.3
1.5
UNIT
μA
nA
V
S
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off) tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet D18663EJ2V0DS


Part Number NP60N04MUG
Description N-CHANNEL POWER MOS FET
Maker Renesas
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