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R1LP0408CSP-7LC - 4M SRAM

Download the R1LP0408CSP-7LC datasheet PDF. This datasheet also covers the R1LP0408CSP-5SC variant, as both devices belong to the same 4m sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The R1LP0408C-C is a 4-Mbit static RAM organized 512-kword × 8-bit.

R1LP0408C-C Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell).

Key Features

  • Single 5 V supply: 5 V ± 10%.
  • Access time: 55/70 ns (max).
  • Power dissipation:  Active: 10 mW/MHz (typ)  Standby: 4 µW (typ).
  • Completely static memory.  No clock or timing strobe required.
  • Equal access and cycle times.
  • Common data input and output.  Three state output.
  • Directly TTL compatible.  All inputs and outputs.
  • Battery backup operation.
  • Operating temperature:.
  • 20 to +70°C Rev.1.00, Aug.01.2003,.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (R1LP0408CSP-5SC-Renesas.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
R1LP0408C-C Series 4 M SRAM (512-kword × 8-bit) REJ03C0077-0100Z Rev. 1.00 Aug.01.2003 Description The R1LP0408C-C is a 4-Mbit static RAM organized 512-kword × 8-bit. R1LP0408C-C Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). The R1LP0408C-C Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-pin TSOP II. Features • Single 5 V supply: 5 V ± 10% • Access time: 55/70 ns (max) • Power dissipation:  Active: 10 mW/MHz (typ)  Standby: 4 µW (typ) • Completely static memory.  No clock or timing strobe required • Equal access and cycle times • Common data input and output.