R5F11AGJANB Overview
(Notification to Interrupt and/or reset function) • Power-on reset (POR) monitor/generator <R> 16-bit RL78-S2 CPU Core • CISC Architecture (Harvard) with 3-stage pipeline • Minimum instruction execution time: Can be changed • 128 KB / 192KB / 256 KB (Block size: 1 KB) • On-chip single voltage flash memory with protection • Internal voltage reference (1.45 V) and temperature sensorNote Note Can be selected only in HS (high-speed main) mode from block erase/writing • Self-programming with secure boot swap function and flash shield window function Safety Functions • ply with the IEC60730 and IEC61508 safety standards Data Flash Memory • Data Flash with background operation • Data flash size: 8 KB size (Erase block size: 1 KB) • Erase Cycles: 1 Million (typ.) • Erase/programming voltage: 1.8 V to 3.6 V General Purpose I/O
R5F11AGJANB Key Features
- RF transmitter active: 4.3 mA (TYP.)
- Up to 4 fully programmable channels
- RF receiver active: 3.5 mA (TYP.)
- Transfer unit: 8- or 16-bit
- RF sleep (POWER_DOWN mode) operation: 0.3 μA
- Simplified I2C×2
- CSI (7-, 8-bit) ×2
- Bluetooth v4.2 Specification (Low Energy Single mode)
- UART (7-, 8-, 9-bit) ×2
- 2.4 GHz ISM Band, GFSK modulation, TDMA/TDD