R5F11MPE Datasheet | Renesas

Features Ultra-low power consumption technology - VDD = single power supply voltage of 1.8 to 3.6 V - HALT mode - STOP mode - SNOOZE mode RL78 CPU core - CISC architecture with 3-stage pipeline - Minimum instruction execution time: Can be changed from high speed (0.04167 s: @ 24 MHz operation with high-speed on-chip oscillator clock) to ultra-low speed (30.5 s: @ 32.768 k Hz operation with subsystem clock) - Multiply/divide and multiply/accumulate instructions are supported. - Address space: 1 MB - General-purpose registers: (8-bit register  8)  4 banks - On-chip RAM: 5.5 KB Code flash memory - Code flash memory: 48 to 128 KB - Block size: 1 KB - Prohibition of block erase and rewriting (security function) - On-chip debug function - Self-programming (with boot swap function/flash shield window function) Data flash memory - Data flash memory: 8 KB - Background operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. - Number of rewrites: 1,000,000 times (TYP.) - Voltage of rewrites: VDD = 1.8 to 3.6 V High-speed on-chip oscillator - Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz - High accuracy: ±1.0% (VDD = 1.8 to 3.6 V, TA = -20 to +85C) Operating ambient temperature - TA = -40 to +85C (A: Consumer applications) Power management and reset function - On-chip power-on-reset (POR) circuit - On-chip voltage detector (LVD) (Select interrupt and reset from 10 levels) Data transfer controller (DTC) - Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode - Activation sources: Activated by interrupt sources (30 sources). - Chain transfer function Event link controller (ELC) - Event signals of 22 types can be linked to the specified peripheral...