R5F52105ADFG
Key Features
- On-chip data flash memory Eight Kbytes, reprogrammable up to TBD times Erasing and programming impose no load on the CPU
- On-chip SRAM, no wait states 20- to 64-Kbyte size capacities
- DMA DMACA: Incorporates four channels DTC: Four transfer modes
- ELC Module operation can be initiated by event signals without going through interrupts. Modules can operate while the CPU is sleeping
- Reset and supply management Nine types of reset, including the power-on reset (POR) Low voltage detection (LVD) with voltage settings
- Independent watchdog timer 125-kHz on-chip low-speed oscillator produces a dedicated clock signal to drive IWDT operation
- External address space Four CS areas (4 × 16 Mbytes) 8- or 16-bit bus space is selectable per area
- 10-bit D/A converter
- Programmable I/O ports 5-V tolerant, open drain, input pull-up, switching of driving ability
- MPC Multiple locati
