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R5F521A6BGFN - MCUs

This page provides the datasheet information for the R5F521A6BGFN, a member of the R5F521A8BDFP MCUs family.

Description

CPU CPU Maximum operating frequency: 50 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Ac

Features

  • 32-bit RX CPU core.
  • Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz.
  • Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations.
  • Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle).
  • Fast interrupt.
  • CISC Harvard architecture with 5-stage pipeline.
  • Variable-length instructions, ultra-compact code.
  • Memory protection unit.
  • On-ch.

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Full PDF Text Transcription

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Datasheet RX21A Group Renesas MCUs 50-MHz 32-bit RX MCUs, 78 DMIPS, 24-bit ∆Σ A/D Converter, up to 512-KB flash memory, IrDA, 10-bit A/D, 10-bit D/A, DEU, ELC, MPC, RTC; up to 9 comms interfaces R01DS0129EJ0110 Rev.1.10 Aug 28, 2014 Features ■ 32-bit RX CPU core  Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz  Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations  Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with 5-stage pipeline  Variable-length instructions, ultra-compact code  Memory protection unit  On-chip debugging circuit ■ Low power design and architecture  Operation from a single 1.
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